In order to more fully appreciate the invention disclosed herein, it is useful to first explain four concepts relevant to integrated circuit design: the relationship of functional block size to yield, the hierarchical nature of integrated circuit design, the use of auto-place-route (APR) tools, and the use of spare cells to make engineering changes (ECs) to integrated circuit designs.
There exists constant market pressure to reduce the cost of integrated circuits. One large factor in the cost of integrated circuits is the yield. Integrated circuits are manufactured as a two-dimensional array of individual integrated circuit dies on a semiconductor wafer. When the wafer has been processed to form the integrated circuit dies, the wafer is cut up to separate the individual dies. Because wafers have flaws, some percentage of the dies in the array will be non-functional. The yield is the ratio of functional dies to the total dies produced.
One large factor in determining the yield is the size of each individual die on the wafer. This is because the wafer flaws are distributed relatively evenly across the wafer, and a single flaw may be sufficient to render an individual die non-functional. Hence, as the size of the die increases, the probability that a die will have one or more flaws and be non-functional increases. At the extreme, a die so large that it takes up the entire wafer, such that only one die can fit on a wafer, would result in a yield approximating 0%. A large factor in determining the die size is how densely the designers are able to place on the die the constituent circuit elements that make up the integrated circuit design.
When engineers design a complex integrated circuit, such as a microprocessor, they design it using a hierarchical approach. That is, they break the design down into high-level pieces that connect together to form the design. The high-level pieces are further broken down into yet smaller pieces that connect together to form the high-level pieces. This hierarchical breakdown may continue such that there are several levels in the hierarchy. The hierarchical approach has the advantage of making the complexity of the design manageable and achievable. The hierarchical approach also has the advantage of enabling different engineers to design different pieces of the design.
At the highest level, the design is made up of multiple pieces commonly referred to as “functional blocks” that are connected together to form the integrated circuit. For example, a microprocessor is made up of functional blocks such as arithmetic logic units, register files, cache memories, floating-point units, instruction translators, etc. The functional blocks have inputs and outputs that are coupled together to form the microprocessor design.
The functional blocks are themselves made up of multiple smaller pieces commonly referred to as “cells.” Examples of cells are logic gates, (e.g., AND, OR, NAND, NOR), flip-flops, multiplexers, registers, comparators, counters, etc. The cells have inputs and outputs that are coupled together to form a functional block. The cells may be standard cells chosen from a library of common cells, or the cells may be custom-designed cells.
When engineers design a block, they typically focus first on which cells need to be included in the block and how the cells in the block will be connected logically, that is, which inputs will be connected to which outputs. Next, they focus on how the included cells will be physically placed within the block and how their inputs and outputs will be connected physically. There are essentially two methods of physically placing the cells within a functional block. One way is for the designers themselves to physically place the cells within the functional block. This type of functional block is commonly referred to as a custom block. An example of a custom block is a high-density memory cell, such as a dynamic random access memory (DRAM) cell.
A second method of physically placing the cells of a functional block is to employ computer-aided design software tools. These tools are commonly referred to as auto-place-route (APR) tools, and functional blocks whose placement is performed by APR tools are commonly referred to as APR blocks. APR tools take as input the list of cells that make up the block (including their physical area and input/output specifications), information that specifies how the cells are to be connected together, and a boundary of the block within which the tool is to place the cells. APR tools attempt to place the cells as densely as possible, while also taking into account the connectivity information for wire routing purposes, and output a physical layout, or placement, of the block and a specification of the physical location of the wires connecting the cell inputs and outputs.
Typically, a user of an APR tool specifies the APR block boundary input such that the area of block is around 5% to 15% more than the sum of the areas of the individual cells that make up the block. The extra area, or “wiggle-room”, is necessary because the cells are not uniform in shape. Thus, without wiggle-room, the APR tool would never fit all the cells into the block boundary. In addition, placing the cells may be very complex and require large amounts of time to perform, even running the APR tools on today's powerful computers. The more wiggle-room allotted, the faster the APR tool can place the cells. As a result of the wiggle-room added to the boundary, there will be unused space within the block that is not taken up by cells. This unused space is commonly referred to as “white space,” which is wasted space on the die. The more white space within the functional blocks of an integrated circuit, the larger the die size, resulting in lower yields.
Because an integrated circuit product can be very complex, over the product's lifetime it is often necessary to make small changes to its design. These small changes are commonly referred to as an “engineering change” or “EC.” Probably the most common cause of an EC is a design flaw or “bug” in the product design that needs to be fixed.
Some ECs may simply require the existing cells to be rewired together in a manner slightly different from the previous design. However, other ECs require new cells to be added and connected in with the existing cells. Knowing this, designers include extra cells, referred to as “spare cells,” within a functional block in addition to the necessary cells, referred to as “functional cells.” The spare cells are capable of performing the same function as functional cells of the same type, such as logic gates or multiplexers, but the inputs and outputs of the spare cells are not connected to other cells in the block. If new cells are needed subsequently to make an EC, then the spare cells are connected to the original functional cells as needed to make the change.
Including spare cells within functional blocks is particularly advantageous in reducing the time and cost required to make an EC. During the manufacture of a complex integrated circuit, it is not uncommon to perform on the order of 100 process steps that are performed over the course of a few weeks. Each process step adds something toward the creation of the integrated circuit dies on the wafer, such as depositing a microscopically thin layer of semiconductor or metal material. The early stages of the process are the most time-consuming and expensive of the steps. These early steps generally define the location of the individual semiconductor devices, such as transistors, that make up the cells. The later process steps are faster, cheaper, and easier to perform, and generally define the location of the wires that connect the transistors, cells, and functional blocks of the integrated circuit.
Consequently, an EC that requires the addition of new transistors or cells is much more costly than an EC that does not require the addition of new transistors or cells, but merely requires rewiring already existing transistors or cells. Placing spare cells into a functional block can greatly increase the likelihood that an EC will only require rewiring.
One reason an EC that does not require the addition of new transistors or cells is less costly is due to the fact that when the wafers are manufactured with the original design (later found to require changing), some of the wafers that have not yet had the wire definition steps performed on them may be set aside, so that when an EC needs to be made, the wire definition steps of the process may be performed to connect in spare cells as needed. This will result in the production of at least some dies with the EC made so that the EC can be tested before being put into mass production. In this scenario, the spare cells are used in a manner to test out bug fixes in a relatively quick manner analogous to the well-known practice of using “white wires” to fix bugs on a circuit board.
In another scenario, assume it is discovered that an integrated circuit is not functioning properly, and the behavior of the circuit is such that the designers believe there is a design flaw, but do not yet know what the bug is or how to fix it. Immediately, wafers could begin being fabricated through the process steps up to, but not including, the wire definition steps while the designers determine the bug and design a fix for the bug using spare cells. Once the bug fix is designed, the final wire definition steps of the process may be performed to connect in the spare cells as needed. This course of action can result in the saving of perhaps two or three weeks, which may be extremely valuable in terms of avoiding lost revenue, particularly in an industry where time-to-market is critical.
Currently, APR block designers determine the block boundary area to provide as input to an APR tool by adding the total functional cell area (i.e., the sum of the areas of the individual functional cells in the block), the area needed for spare cells (typically about 5%–15% of the total functional cell area), and the area needed for wiggle-room to enable the APR tool to effectively place the cells (typically about 5%–15% of the sum of the total functional cell area and the spare cell area).
The disadvantage of the conventional method is that it generates relatively large amounts of white space within APR blocks, namely the wiggle-room area, which results in larger die sizes, which in turn results in lower yields than a completely efficiently placed integrated circuit. Therefore, what is needed is a method for reducing the white space in integrated circuit APR blocks.